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august 2006 rev 6 1/29 1 m41t11 serial real time clock with 56 bytes of nvram feature summary counters for seconds, minutes, hours, day, date, month, years and century 32khz crystal oscillator integrating load capacitance (12.5pf) providing exceptional oscillator stability and high crystal series resistance operation serial interface supports i 2 c bus (100khz protocol) ultra-low battery supply current of 0.8a (typ@3v) 2.0 to 5.5v clock operating voltage automatic switch -over and deselect circuitry 56 bytes of general purpose ram software clock calibration to compensate crystal deviation due to temperature automatic leap year compensation operating temperature of ?40 to 85c packaging includes a 28-lead soic and snaphat ? top (to be ordered separately; 3.3v to 5.0v supply voltage only) 8 1 so8 (m) snaphat (sh) battery & crystal 28 1 soh28 (mh) www.st.com
contents m41t11 2/29 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 bus not busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 start data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 preferred initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m41t11 list of tables 3/29 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. so8 ? 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 23 table 12. soh28 ? 28-lead plastic small outline, battery snaphat package mech. data . . . . . . . . . . 24 table 13. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data . . . . . . . 25 table 14. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data. . . . . . 26 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of figures m41t11 4/29 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 8-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. 28-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 8. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. ac testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. so8 ? 8-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. soh28 ? 28-lead plastic small outline, battery snaphat package outline . . . . . . . . . . . . . . 24 figure 18. sh ? 4-pin snaphat housing for 48mah battery & crystal package outline. . . . . . . . . . . 25 figure 19. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline . . . . . . . . . 26
m41t11 summary description 5/29 1 summary description the m41t11is a low power serial real time clock with 56 bytes of nvram. a built-in 32.768khz oscillator (external crystal controlled) and the first 8 bytes of the ram are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. addresses and data are transferred serially via a two-line bi-directional bus. the built-in address register is incremented automatically after each write or read data byte. the m41t11 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. the energy needed to sustain the ram and clock operations can be supplied from a small lithium coin cell. typical data retention time is in excess of 5 years with a 50ma/h 3v lithium cell. the m41t11 is supplied in 8 lead plastic small outline package or 28 lead snaphat ? package. the 28-pin, 330mil soic provides sockets with gol d plated contacts at both ends for direct connection to a separate snaphat housing containing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery/crystal package (i.e. snaphat) part number is ?m4txx- br12sh? (see table 16 on page 27 ). caution: do not place the snaphat battery/crystal package ?m4txx-br12sh? in conductive foam since this will drain the lithium button-cell battery. figure 1. logic diagram ai01000 osci v cc m41t11 v ss scl osco sda ft/out v bat
summary description m41t11 6/29 figure 2. 8-pin soic connections figure 3. 28-pin soic connections table 1. signal names osci oscillator input ocso oscillator output ft/out frequency test/output driver (open drain) sda serial data address input/output scl serial clock v bat battery supply voltage v cc supply voltage v ss ground 1 sda v ss scl ft/out osco osci v cc v bat ai01001 m41t11 2 3 4 8 7 6 5 ai03606 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 nc v ss nc nc nc v cc m41t11 nc nc nc nc nc nc nc nc nc nc nc sda nc scl nc nc nc nc nc ft/out nc nc
m41t11 summary description 7/29 figure 4. block diagram ai02566 seconds oscillator 32.768 khz voltage sense and switch circuitry serial bus interface divider control logic address register minutes century/hours day date month year control ram (56 x 8) osci osco ft/out v cc v ss v bat scl sda 1 hz
operation m41t11 8/29 2 operation the m41t11 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 64 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: seconds register 2 nd byte: minutes register 3 rd byte: century/hours register 4 th byte: day register 5 th byte: date register 6 th byte: month register 7 th byte: years register 8 th byte: control register 9 th - 64 th bytes: ram the m41t11 clock continually monitors v cc for an out of tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at th is time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v so , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. upon power-up, the device switches from battery to v cc at v so and recognizes inputs. 2.1 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be inte rpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy. both data and clock lines remain high. 2.1.2 start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition.
m41t11 operation 9/29 2.1.3 stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition, a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. th e device that controls the message is called ?master?. the devices that are controlled by the master are called ?slaves?. 2.1.5 acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. figure 5. serial bus data transfer sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition
operation m41t11 10/29 figure 6. acknowledgement sequence figure 7. bus timing requirements sequence 1. p = stop and s = start ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
m41t11 operation 11/29 table 2. ac characteristics 2.2 read mode in this mode, the master reads the m41t11 slave after setting the slave address (see figure 8 ). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address a n is written to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/w = 1). at this point, the master transmitter becomes th e master receiver. the data by te which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge bit. the m41t11 slave transmitter will now place t he data byte at address a n + 1 on the bus. the master receiver reads and acknowledges the new byte and the address pointer is incremented to a n + 2. this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. an alternate read mode may also be implemented, whereby the master reads the m41t11 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 10 on page 12 ). symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min max unit f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4 s t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 4s t su:sta start condition setup time (only relevant for a repeated start condition) 4.7 s t su:dat data setup time 250 ns t hd:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined region (300ns max.) of the falling edge of scl. data hold time 0 s t su:sto stop condition setup time 4.7 s t buf time the bus must be free before a new transmission can start 4.7 s
operation m41t11 12/29 figure 8. slave address location figure 9. read mode sequence figure 10. alternate read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
m41t11 operation 13/29 2.3 write mode in this mode the master transmitter transmits to the m41t11 slave receiver. bus protocol is shown in figure 8 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addr essed device that word address an will foll ow and is to be wr itten to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41t11 slave receiver will send an ackno wledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 7 on page 10 ). 2.4 data retention mode with valid v cc applied, the m41t11 can be accessed as described above with read or write cycles. should the supply voltage decay, the m41t11 will automatically desele ct, write protecting itself when v cc falls (see figure 15 ). figure 11. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
clock operation m41t11 14/29 3 clock operation the eight byte clock register (see ta bl e 3 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 2 (hours register) contain the century enable bit (ceb) and th e century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its init ial state). if ceb is set to a '0', cb will not toggle. bits d0 through d2 of register 3 contain the day (day of week). registers 4, 5 and 6 contain the date (day of month), month and years. the final register is the control register (this is described in the clock calibration section). bit d7 of register 0 contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the devi ce is expected to spend a significant amount of time on the shelf, the oscillator may be st opped to reduce current drain. when reset to a '0' the oscillator restarts within one second. note: i n order to guarantee oscillator star t-up after the initial power-up, set the st bit to a '1,' then reset this bit to a '0.' this sequence enables a ?kick start? circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. the seven clock registers may be read one byte at a time, or in a sequential block. the control register (address location 7) may be accessed independently. provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. if a clock addr ess is being read, an update of the clock registers will be delayed by 250ms to allow the read to be completed before the update occurs. this will prevent a transition of data during the read. note: this 250ms delay affects only the clock register update and does not alter the actual clock time.
m41t11 clock operation 15/29 3.1 clock calibration the m41t11 is driven by a quartz contro lled oscillator with a nom inal frequency of 32,768hz. the devices are test ed not to exceed 35 ppm (p arts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m41t11 improves to better than 2 ppm at 25c. the oscillation rate of any cryst al changes with temperature (see figure 12 on page 17 ). most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the m41t11 design, however, employs periodic counter correction. the calibration circuit adds or subt racts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 13 on page 17 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register (addr 7). this byte can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of table 3. register map (1) 1. keys: s = sign bit ft = frequency test bit st = stop bit out = output level x = don?t care ceb = century enable bit cb = century bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 x 10 minutes minutes minutes 00-59 2ceb (2) 2. when ceb is set to '1', cb will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set). when ceb is set to '0', cb will not to ggle.when ceb is set to '1', cb will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set). when ceb is set to '0', cb will not toggle. cb 10 hours hours century/hours 0-1/00-23 3xxxxx day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out ft s calibration control
clock operation m41t11 16/29 adjustment per calibration step in the calibration register. assu ming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ? 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41t11 may require. the first involves simply setting the cl ock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate hi s clock as his environment may require, even after the final product is packag ed in a non-user serviceable enclosure. all the designer has to do is provid e a simple utility that acce ssed the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32,768hz, the ft/out pin of the device will toggle at 512hz. any de viation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512. 01024hz would indicate a +20 ppm oscillator frequency error, requiring a ?10(xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. 3.2 output driver pin when the ft bit is not set, the ft/out pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d6 of location 7 is a zero and d7 of location 7 is a ze ro and then the ft/out pin will be driven low. note: the ft/out pin is open drain which requires an external pull-up resistor. 3.3 preferred initial power-on defaults upon initial application of power to the device , the ft bit will be set to a '0' and the out bit will be set to a '1'. all other register bits will initially power-on in a random state.
m41t11 clock operation 17/29 figure 12. crystal accuracy across temperature figure 13. clock calibration ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 ? f = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal positive calibration negative calibration
maximum rating m41t11 18/29 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. table 4. absolute maximum ratings symbol parameter value unit t a ambient operating temperature ?40 to 85 c t stg storage temperature (v cc off, oscillator off snaphat ? ?40 to 85 c soic ?55 to 125 t sld (1)(2) 1. for so package, standard (snpb) l ead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180c for between 90 to 150 seconds). 2. for so package, lead-free (pb-free) lead finish: reflow at peak tem perature of 260c (total thermal budget not to exceed 245c for greater than 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output vo ltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 0.25 w
m41t11 dc and ac parameters 19/29 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 14. ac testing input/output waveform table 5. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t11 unit supply voltage (v cc ) 2.0 to 5.5 (2) 2. supply voltage for soh28 is 3.3v to 5.5v. v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing ref. voltages 0.3v cc to 0.7v cc v ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
dc and ac parameters m41t11 20/29 table 6. capacitance symbol parameter (1)(2) 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. min max unit c in input capacitance (scl) 7 pf c out (3) 3. outputs deselected. output capacitance (sda, ft/out) 10 pf t lp low-pass filter input time constant (sda and scl) 250 1000 ns table 7. dc characteristics symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch frequency = 100khz 300 a i cc2 supply current (standby) scl, sda = v cc ? 0.3v 70 a v il input low voltage ?0.3 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.5 v v ol output low voltage i ol = 3ma 0.4 v pull-up supply voltage (open drain) ft/out 5.5 v v bat (2) 2. stmicroelectronics recommends the rayovac br1225 or br1632 (or equivalent) as the battery supply. battery supply voltage 2.5 (3) 3. after switchover (v so ), v bat (min) can be 2.0v for crystal with r s = 40k ? . 33.5 (4) 4. for rechargeable back-up, v bat (max) may be considered v cc . v i bat battery supply current t a = 25c, v cc = 0v, oscillator on, v bat = 3v 0.8 1 a table 8. crystal electrical characteristics symbol parameter (1)(2)(3) 1. these values are externally supp lied if using the so8 package. stmi croelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru- hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temp erature operations. kds can be cont acted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the m41t11. ci rcuit board layout consider ations for the 32.768khz crystal of minimum trace lengths and isolation from rf generating signal s should be taken into account. 3. all snaphat ? battery:crystal tops m eet these specifications. min typ max unit f o resonant frequency 32.768 khz r s series resistance 60 k ? c l load capacitance 12.5 pf
m41t11 dc and ac parameters 21/29 figure 15. power down/up mode ac waveforms table 9. power down/up ac characteristics symbol parameter (1)(2) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. v cc fall time should not exceed 5mv/s. min max unit t pd scl and sda at v ih before power down 0 ns t rec scl and sda at v ih after power up 10 s table 10. power down/up trip points dc characteristics symbol parameter (1) (2) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. all voltages referenced to v ss . min typ max (3) 3. in 3.3v application, if initial battery voltage is 3.4v, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switc hover/deselection for v cc ? 10% operation. unit v so (4) 4. switch-over and deselect point. battery back-up switchover voltage v bat ? 0.80 v bat ? 0.50 v bat ? 0.30 v ai00596 v cc trec tpd v so sda scl don't care
package mechanical information m41t11 22/29 6 package mechanical information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
m41t11 package mechanical information 23/29 figure 16. so8 ? 8-lead plastic small outline package outline 1. drawing is not to scale. table 11. so8 ? 8-lead plastic small outline package mechanical data symbol millimetres inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical information m41t11 24/29 figure 17. soh28 ? 28-lead plastic small outline, battery snaphat package outline 1. drawing is not to scale. table 12. soh28 ? 28-lead plastic small outline, battery snaphat package mech. data symb mm inches typ min max typ min max a3.050.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 1 h a cp be a2 eb
m41t11 package mechanical information 25/29 figure 18. sh ? 4-pin snaphat housing for 48mah battery & crystal package outline 1. drawing is not to scale. table 13. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data symb mm inches typ min max typ min max a9.780.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
package mechanical information m41t11 26/29 figure 19. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline 1. drawing is not to scale. table 14. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-b a1 a d e ea eb a2 b l a3
m41t11 part numbering 27/29 7 part numbering caution: do not place the snaphat battery package ?m 4txx-br12sh? in conductive foam as it will drain the lithium button-cell battery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 15. ordering information scheme example: m41t 11 m 6 e device type m41t supply voltage 11 = v cc = 2.0 to 5.5v (1) 1. soh28 supply voltage is 3.3v to 5.5v. package m = so8 (150mil width) mh (2) = soh28 2. the soic package (soh28) requires the snaphat ? battery package which is ordered separately under the part number ?m4txx-br12shx? in plastic tube or ?m4txx-br12s hxtr? in tape & reel form (see table 16 ). temperature range 6 = ?40 to 85c shipping method for so8: e = lead-free package (ecopack ? ), tubes f = lead-free package (ecopack ? ), tape & reel for soh28: e = lead-free package (ecopack ? ), tubes f = lead-free package (ecopack ? ), tape & reel table 16. snaphat battery table part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
revision history m41t11 28/29 8 revision history table 17. revision history date revision revision changes march 1999 1.0 first issue 12/23/99 1.1 soh28 package added 07/25/00 1.2 crystal electrical characteristics: r s max changed ( ta bl e 8 ) 12/12/00 1.3 edit v so ( ta b l e 1 0 ) 01/24/01 2.0 reformatted 2/27/01 3.0 document status changed 07/17/01 3.1 change to dc and ac characteristics ( ta bl e 7 , ta bl e 2 ); added temp/voltage info. to ( ta b l e 6 , ta b l e 7 , ta bl e 8 , ta bl e 2 , ta bl e 9 , ta bl e 1 0 ); added snaphat battery table ( ta bl e 1 6 ). 11/27/01 3.2 features, (page 1); dc characteristics ( ta b l e 7 ); crystal electrical ( ta bl e 8 ); power down/up trip points ( ta b l e 1 0 ) changes; add table footnotes ( ta b l e 5 , ta b l e 1 0 , ta b l e 1 5 ) 01/21/02 3.3 fix table footnotes ( ta b l e 7 , ta bl e 8 ) 05/01/02 3.4 modify reflow time and temperature footnote ( ta bl e 4 ) 07/03/02 3.5 modify ?clock operation? text, crystal electrical characteristics table footnote ( ta b l e 8 ) 11/07/02 3.6 correct figure name in feature summary on page 1 ; 15-jun-04 4.0 reformatted; added lead-free information; updated characteristics ( figure 12 ; ta bl e 4 , ta bl e 7 , ta bl e 1 5 ) 14-dec-04 5.0 correct footnote ( ta b l e 8 ) 22-aug-2006 6 changed document to new template; changed title on page 1; re-ordered text and amalgamated figures in feature summary on page 1 ; updated package mechanical data in section 6: package mechanical information ; amended footnotes in ta bl e 2 and ta b l e 9 ; ta b l e 1 5 ecopack compliant; small text changes for entire document
m41t11 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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